Industry practices for testing systems-on-a-chip (SOCs) require expensive automated test equipment (ATE) whose cost is directly proportional to the number of channels, speed, and operational memory available per test input-output (TO) channel. As chip sizes grow, requirements increase for memory per IO channel.
In many cases, additional test IO channels are not available nor does the speed of test channels improve. With 2.5D and 3D chips becoming more prevalent the IO channels available for test have further decreased. Scan compression schemes from various electronic design automation (EDA) tool vendors aim to achieve lower test data requirements, but they come at the cost of poor test coverage or vendor-specific design customization.
Correlating ATE to system-level test failures is another challenge. Executing structural tests at system level is expensive, which often makes this process impractical. There have been some efforts to enable structural test at system-level but these utilize special-purpose test interfaces and are not broadly applicable. Existing solutions tend to incur high latency making them expensive to use with multiple fault models or test programs.
Automotive and high-performance computing (HPC) applications require tests to execute in the field to help ensure safety and reliability. Structural tests provide high test coverage compared to functional patterns and are most suited to satisfy the requirements of these applications. Existing schemes for in-field structural testing are limited by long execution times and/or data storage requirements.